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A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The list presented here is sorted by departments, within departments alphabetically by the Course title. The departments are listed alphabetically by the Department code.

Courses


18103 Department of Digital Design
Course code Course title Extent of teaching
 Completion
 Semester
 Credits
 Guarantor Instructors
MI-PVS Advanced embedded systems 2P+2C Z,ZK Z 4
NI-PVS Advanced embedded systems 2P+2C Z,ZK Z 4
BIE-ZRS.21 Basics of System Control 2P+2C Z,ZK Z,L 5 Hyniová K. Hyniová K.
BI-ZRS Basics of System Control 2P+2C Z,ZK Z 4
BI-ZRS.21 Basics of System Control 2P+2C Z,ZK Z 5 Hyniová K. Hyniová K.
BIE-ZRS Basics of Systems Control 2P+2C Z,ZK L 4
MI-KOP Combinatorial optimization 2P+2C Z,ZK Z 5
NIE-KOP Combinatorial Optimization 3P+1C Z,ZK Z 6 Fišer P. Fišer P., Schmidt J.
NI-KOP Combinatorial Optimization 2P+2C Z,ZK Z 6 Schmidt J. Schmidt J.
MI-ARI Computer arithmetic 2P+1C Z,ZK Z,L 4
NI-ARI Computer arithmetic 2P+1C Z,ZK Z,L 4 Kubalík P. Kubalík P.
NIE-ARI Computer arithmetic 2P+1C Z,ZK Z,L 4 Pluháček A. Kubalík P.
BIE-SCE1 Computer Engineering Seminar I 2C Z Z 4 Kubátová H. Kubátová H., Skrbek M.
BI-SCE1 Computer Engineering Seminar I 2C Z L,Z 4 Kubátová H. Kubátová H.
BIE-SCE2 Computer Engineering Seminar II 2C Z L 4 Kubátová H. Kubátová H.
BI-SCE2 Computer Engineering Seminar II 2C Z L,Z 4 Kubátová H. Kubátová H.
MI-SCE2 Computer Engineering Seminar Master II 2C Z L,Z 4
NIE-SCE2 Computer Engineering Seminar Master II 2C Z L 4 Kubátová H. Kubátová H.
NI-SCE2 Computer Engineering Seminar Master II 2C Z L,Z 4 Kubátová H. Kubátová H.
MI-SCE1 Computer Engineering Seminar Master I 2C Z L,Z 4
NIE-SCE1 Computer Engineering Seminar Master I 2C Z Z 4 Kubátová H. Kubátová H.
NI-SCE1 Computer Engineering Seminar Master I 2C Z L,Z 4 Kubátová H.
BI-SAP Computer Structure and Architecture 2P+1R+2C Z,ZK L 6
BI-SAP.21 Computer Structure and Architecture 2P+1R+2C Z,ZK L 5 Kubátová H. Borecký J., Kohlík M., Kubátová H.
BIK-SAP Computer Structure and Architecture 13KP+4KC Z,ZK L 6
BIK-SAP.21 Computer Structure and Architecture 14KP+6KC Z,ZK L 5 Daňhel M. Daňhel M.
BIE-SAP Computer Structures and Architectures 2P+1R+2C Z,ZK L 6
BIE-SAP.21 Computer Structures and Architectures 2P+1R+2C Z,ZK L 5 Fišer P. Fišer P.
BIE-JPO Computer Units 2P+2C Z,ZK Z 5
BIE-JPO.21 Computer Units 2P+2C Z,ZK Z 5 Kubalík P. Kubalík P.
BI-JPO Computer Units 2P+2C Z,ZK Z 5
BI-JPO.21 Computer Units 2P+2C Z,ZK Z 5 Kubalík P. Kubalík P.
MI-NFA Design for the FPGA and ASIC Technology 2P+1C Z,ZK Z 4
MI-NFA.16 Design for the FPGA and ASIC Technology 2P+1C Z,ZK Z 5
BI-CAO Digital and Analog Circuits 2P+2C Z,ZK Z 5
BIE-CAO Digital and Analog Circuits 2P+2C Z,ZK Z 5
BIK-CAO Digital and Analog Circuits 13KP+4KC Z,ZK Z 5
NIE-SIM Digital Circuit Simulation and Verification 2P+1C Z,ZK L 5 Kohlík M. Kohlík M.
NI-SIM Digital Circuit Simulation and Verification 2P+1C Z,ZK L 5 Kohlík M. Kohlík M.
MI-SIM.16 Digital Circuit Simulation 2P+1C Z,ZK L,Z 5
NIE-EHW Embedded Hardware 2P+1C Z,ZK Z 5 Schmidt J. Schmidt J.
NI-EHW Embedded Hardware 2P+1C Z,ZK Z 5 Schmidt J. Schmidt J.
NI-BVS Embedded Security 2P+2C Z,ZK L 5 Novotný M. Novotný M.
NIE-BVS Embedded Security 2P+2C Z,ZK L 5 Novotný M. Novotný M.
NIE-ESW Embedded Software 2P+1C Z,ZK Z 5 Kubátová H. Kubátová H., Skrbek M.
NI-ESW Embedded Software 2P+1C Z,ZK Z 5 Kubátová H. Kubátová H., Skrbek M.
BIE-VES Embedded Systems 2P+2C Z,ZK L 5
BIE-VES.21 Embedded Systems 2P+2C Z,ZK L 5 Skrbek M. Skrbek M.
BIK-VES Embedded Systems 13KP+4KC Z,ZK L 5
BI-VES Embedded Systems 2P+2C Z,ZK L 5
BI-VES.21 Embedded Systems 2P+2C Z,ZK L 5 Skrbek M. Skrbek M.
MI-BKO.16 Error Control Codes 2P+1C Z,ZK L 5
NI-BKO Error Control Codes 2P+1C Z,ZK L 5 Pluháček A. Kubalík P., Pluháček A.
NIE-BKO Error Control Codes 2P+1C Z,ZK L 5 Kubalík P. Kubalík P.
BI-HAM HW accelerated network traffic monitoring 2P+1C KZ L 4 Čejka T. Čejka T., Hynek K.
BI-ZIVS Intelligent Embedded System Fundamentals 1P+3C KZ Z 4 Skrbek M. Skrbek M.
MI-IVS Intelligent embedded systems 1P+3C KZ L 4
NI-IVS Intelligent embedded systems 1P+3C KZ L 4 Skrbek M. Skrbek M.
BI-ARD Interactive applications on Arduino 3C KZ L 4 Hülle R.
MI-OLI Linux Drivers 2P+2C Z,ZK L 4
NI-OLI Linux Drivers 2P+2C Z,ZK L 4 Skrbek M. Skrbek M.
BIE-MPP.21 Methods of interfacing peripheral devices 2P+2C Z,ZK Z 5 Skrbek M. Skrbek M.
BI-MPP Methods of interfacing peripheral devices 2P+2C Z,ZK Z 4 Skrbek M. Skrbek M.
BI-MPP.21 Methods of interfacing peripheral devices 2P+2C Z,ZK Z 5 Skrbek M. Skrbek M.
BIE-PNO Practical Digital Design 2P+2C KZ Z 5 Novotný M. Novotný M.
BIE-PNO.21 Practical Digital Design 2P+2C KZ Z 5 Novotný M. Novotný M.
BI-PNO Practical Digital Design 2P+2C KZ Z 5 Novotný M. Novotný M.
BI-PNO.21 Practical Digital Design 2P+2C KZ Z 5 Novotný M. Novotný M.
MI-PAA Problems and Algorithms 2P+1R+1C Z,ZK Z 5
BIE-SRC.21 Real-time systems 2P+2C Z,ZK Z 5 Kubátová H. Kubátová H.
BI-SRC Real-time systems 2P+2C KZ Z 4 Kubátová H. Kubátová H.
BI-SRC.21 Real-time systems 2P+2C Z,ZK Z 5 Kubátová H. Kubátová H.
MI-BHW Security and Hardware 2P+2C Z,ZK L 4
MI-BHW.16 Security and Hardware 2P+2C Z,ZK L 5
PI-SCN Seminars on Digital Design 2P+1C ZK Z,L 4 Fišer P. Fišer P.
NIE-HSC Side-Channel Analysis in Hardware 2P+2C Z,ZK Z 4 Miškovský V. Miškovský V., Socha P.
NI-HSC Side-Channel Analysis in Hardware 2P+2C Z,ZK Z 4 Miškovský V. Miškovský V., Socha P.
MI-SOC.16 Systems on Chip 2P+1C Z,ZK Z 5
MI-TES.16 Systems Theory 2P+1C Z,ZK Z 5
NIE-TES Systems Theory 2P+1C Z,ZK Z 5 Ratschan S. Ratschan S.
NI-TES Systems Theory 2P+1C Z,ZK Z 5 Ratschan S. Ratschan S.
BIE-TZP.21 Technological Fundamentals of Computers 2P+2C Z,ZK Z 5 Novotný M. Hyniová K., Novotný M.
BIK-TZP.21 Technological Fundamentals of Computers 14KP+4KC Z,ZK Z 5 Daňhel M., Novotný M. Daňhel M., Hyniová K., Novotný M.
BI-TZP.21 Technological Fundamentals of Computers 2P+2C Z,ZK Z 5 Novotný M. Řezníček J., Novotný M.
MI-TSP Testing and Reliability 2P+2C Z,ZK Z 4
MI-TSP.16 Testing and Reliability 2P+2C Z,ZK Z 5
NIE-TSP Testing and Reliability 2P+2C Z,ZK Z 5 Fišer P. Fišer P.
NI-TSP Testing and Reliability 2P+2C Z,ZK Z 5 Fišer P. Fišer P.
BIE-TUR.21 User Interface Design 2P+2C Z,ZK L 5 Schmidt J. Schmidt J.
BIK-TUR User Interface Design 13KP+4KC Z,ZK L 4
BIK-TUR.21 User Interface Design Z,ZK L 5 Schmidt J. Schmidt J.
BI-TUR User Interface Design 2P+2C Z,ZK L 4
BI-TUR.21 User Interface Design 2P+2C Z,ZK L 5 Schmidt J. Schmidt J.

Page updated 19. 4. 2024, semester: L/2020-1, L/2021-2, Z/2023-4, Z/2024-5, Z/2019-20, Z/2022-3, L/2019-20, L/2022-3, Z/2020-1, Z/2021-2, L/2023-4, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška