A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.
PI-SCN Seminars on Digital Design Extent of teaching: 2P+1C Instructor: Fišer P. Completion: ZK Department: 18103 Credits: 4 Semester: Z,L Annotation:
This subject deals with problems of realization and implementation of digital circuits - both combinational and sequential. Basic means of description of digital circuits and basic logic synthesis and optimization algorithms are described. Basics of EDA (Electronic Design Automation) systems are given, together with combinatorial problems emerging in EDA.
Lecture syllabus:
1. Representations of logic functions 2. Binary decision diagrams (BDDs), structures derived from 3. Other representations of logic functions and digital circuits 4. Two-level minimization 5. Multi-level logic synthesis, decomposition - algebraic methods 6. Multi-level logic synthesis, decomposition - Boolean methods 7. Exploiting don't cares in multi-level logic synthesis and optimization 8. Sequential circuits synthesis. Automata theory. Decomposition, automata realization. Sequential circuits optimization 9. Asynchronous circuits 10. Technology mapping, timing models 11. Contemporary synthesis - ABC 12. Combinatorial problems in EDA systems Seminar syllabus:
1. Binary decision diagrams (BDDs) 2. Two-level functions descriptions. PLA. Espresso and other two-level minimizers 3. Multi-level functions descriptions. Blif. Logic synthesis and optimization tool SIS 4. Logic synthesis and optimization tool ABC 5. SAT problem, solvers. Circuit-SAT conversion 6. Equivalence checking Literature:
Proceedings of conferences of digital design, e.g. DAC, DATE, DDECS, DSD, ISWBP, etc.
G. D. Hachtel, F. Somenzi: "Logic Synthesis and Verification Algorithms", Kluwer Academic Pub, 1996, 564 p. S. Hassoun, T. Sasao, "Logic Synthesis and Verification", Boston, MA, Kluwer Academic Publishers, 2002, 454 p. Requirements:
Digital system design master courses knowledge.
Informace o předmětu a výukové materiály naleznete na https://moodle-vyuka.cvut.cz/course/view.php?id=5040 The course is also part of the following Study plans:
Page updated 20. 4. 2024, semester: L/2023-4, L/2020-1, L/2022-3, L/2021-2, Z/2019-20, Z/2022-3, Z/2020-1, Z/2023-4, L/2019-20, Z/2021-2, Z/2024-5, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška