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A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.

ANI-EHW Embedded Hardware Extent of teaching: 2P+2C
Instructor: Schmidt J. Completion: Z,ZK
Department: 18103 Credits: 5 Semester: L

Annotation:
Předmět poskytuje znalost základních technik a zákonitostí, které řídí konstrukci číslicových zařízení jak malého, tak velkého měřítka. Jsou základem konstrukce pokročilých vestavných systémů, které využívají specializaci své funkce ke konstrukci efektivní hardwarové realizace či podpory výpočtu. Probírají se techniky konstrukce rychlých systémů, jejich standardní vnitřní komunikace, využití přirozeného paralelismu výpočtu ve specializovaných strukturách a systémových architekturách.

Lecture syllabus:
1. Hardware as an implementation platform. Terminology, domains, abstraction levels.
2. Throughput and time in digital systems. Clock domains. System radius
3. System Level and Register Transfer Level specifications. Model-based engineering, system-level models.
4. Parallel computation in dedicated hardware, computation scaling, optimality criteria.
5. Communications in small-radius systems. Transaction protocols.
6. Switching networks. Optimum communication design.
7. Power estimation, power reduction.
8. Communication in large-radius systems. Industrial interfaces. Advanced serial communication.
9. Communication in large-radius systems. Networks on a chip.
10. FPGA technology overview, resources, programming, application.
11. Timing and power management at system level.
12. Processors and FPGAs, cores, SoC
13. FPGA: input and output, signalling standards, serialization

Seminar syllabus:
bude doplněno

Literature:
1. Gu, C.: Building Embedded Systems: Programmable Hardware. Apress, 2016. ISBN 9781484219188.
2. Barkalov, A. - Titarenko, L. - Mazurkiewicz, M.: Foundations of Embedded Systems. Springer, 2019. ISBN 3030119602.
3. Mohit, A.: Embedded System Design: Introduction to SoC System Architecture. Learning Bytes Publishing, 2016. ISBN 0997297204.

Requirements:

Výukové materiály na https://courses.fit.cvut.cz/NI-EHW/

The course is also part of the following Study plans:
Study Plan Study Branch Role Recommended semester
QNI Unspecified Specialisation of Study V 2
ANI-WI Web Engineering VO 2
ANI-SI Software Engineering (in Czech) VO 2
NI-PB.2026 Computer Security V 2
NI-SPOL.2026 Unspecified Specialisation of Study V 2
NI-UI.2026 Artificial Intelligence V 2
NI-PJ.2026 Programming Languages V 2
NI-TI.2026 Computer Science V 2
NI-PSS.2026 Computer Systems and Networks V 2
ANI-MI Business Informatics VO 2
ANI-VG Visual computing and Game design VO 2
ANI-SPOL Unspecified Specialisation of Study VO 2
ANI-ES Embedded systems PS 2


Page updated 18. 8. 2026, semester: Z/2023-4, Z/2021-2, Z/2022-3, L/2025-6, L/2022-3, Z/2025-6, L/2023-4, L/2024-5, Z/2026-7, L/2021-2, L/2026-7, Z/2024-5, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška