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A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.

MI-SIM.16 Digital Circuit Simulation Extent of teaching: 2P+1C
Instructor: Completion: Z,ZK
Department: 18103 Credits: 5 Semester: L,Z

Annotation:
Students gain information regarding the usage of basic tools for the design and simulation of VLSI (very large scale integration) digital circuits (VHDL, Verilog). They also get some knowledge about advanced tools System Verilog & SystemC.

Lecture syllabus:
1. Fundamental simulation principles, abstraction levels of digital circuit description.
2. [5] VHDL: Entities, architectures, overview of data types and corresponding operations, delta delay, inertial delay, transport delay, sequential environment, signal attributes, resolution function, synthesizable constructs of the language, creating user libraries, data-flow description, blocks, guarded blocks, guarded assignment statements, guarded signals, structural description, configuration of structural architectures, creating tests.
3. [4] Verilog: Analogy with VHDL, modules and their interfaces, overview of data types and operations, sequential environment, nondeterministic Verilog behavior, blocking and nonblocking assignments, parallel environment, nets and strengths, synthesizable constructs of the language, modeling structures, primitive elements, creating tests.
4. [2] Modern trends in the area of digital circuit simulation (transaction level modeling, coverage driven testbench, assertions). SystemC & SystemVerilog: overall characteristic of the system. Methods of parallel simulation.

Seminar syllabus:
1. Getting acquainted with the MODELSIM system. Presentation of examples in the VHDL language.
2. Working on the first project.
3. Working on the first project.
4. Working on the second project.
5. Working on the third project.
6. Final evaluation and assessment.

Literature:
Dewey, A. M. Analysis and Design of Digital Systems with VHDL. International Thomson Publishing, 1996. ISBN 0534954103. Cohen, B. VHDL Coding Styles and Methodologies. Springer, 1999. ISBN 0792384741. Ciletti, M. D. Advanced Digital Design with the Verilog HDL. Prentice Hall, 2002. ISBN 0130891614. Bhasker, J. A SystemC Primer. Star Galaxy Publishing, 2004. ISBN 0965039129. Grötker, T., Liao, S., Martin, G., Swan, S. System Design with SystemC. Springer, 2002. ISBN 1402070721.

Requirements:
Design methods for combinational and sequential logic circuits, knowledge of number representations, knowledge of the circuit implementations of basic arithmetic operations.

Informace o předmětu a výukové materiály naleznete na https://courses.fit.cvut.cz/MI-SIM/

The course is also part of the following Study plans:
Study Plan Study Branch/Specialization Role Recommended semester
MI-NPVS.2016 Design and Programming of Embedded Systems PO 1
NI-TI.2018 Computer Science V 1


Page updated 28. 3. 2024, semester: Z/2023-4, L/2019-20, L/2022-3, Z/2019-20, Z/2022-3, L/2020-1, L/2023-4, Z/2020-1, Z,L/2021-2, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška