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A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.

MI-PAP.16 Parallel Computer Architectures Extent of teaching: 2P+1C
Instructor: Completion: Z,ZK
Department: 18104 Credits: 5 Semester: L

Annotation:
The students gain a good overview of present parallel architectures and processors:parallel (ILP) microarchitectures, multithreaded and multicore processors, SoCs and MPSoCs, GPUs, and neural processors. Students also get hands-on experience with programming these systems.

Lecture syllabus:
1. Introduction, compiler optimizations
2. SIMD architectures. programming, data dependency solutions, hiding latency of instructions.
3. VLIW architectures, programming, speculative solutions of data dependences, solutions for exceptions.
4. Homogeneous multi-core architectures, memory subsystem, interrupts, Programming environments and tools for multicore architectures
5. GPU architectures
6. Programming environments and tools for GPUs I 7. Programming environments and tools for GPUs II
8. Programming environments and tools for GPUs III
9. Programming environments and tools for GPUs (OpenCL).
10. Heterogeneous multi-core architectures, shared and local memory, data transfers.
11. Digital signal processors, DSP VLIW architectures.
12. Special parallel architectures, virtual architectures, neural networks. Systems on chip (SoC, NoC), switching networks, synchronous and asynchronous module interconnections.
13. Final prezentation, conclusions

Seminar syllabus:
1. Introduction, assigning projects to students
2. Development tools, technologie OpenMP
3. Project consultation, project presentation I 4. Project consultation
5. Project presentation II
6. Project presentation III, assessment

Literature:
1. El-Rewini, H., Abd-El-Barr, M. ''Advanced Computer Architecture and Parallel Processing''. Wiley-Interscience, 2005. ISBN 0471467405.
2. De Micheli, G., Benini, L. ''Networks on Chips: Technology and Tools''. Morgan Kaufmann, 2006. ISBN 0123705215.
3. Jerraya, A., Wolf, W. ''Multiprocessor Systems-on-Chips''. Morgan Kaufmann, 2004. ISBN 012385251X.
4. Keckler, S. W., Olukotun, K., Hofstee, H. P. ''Multicore Processors and Systems''. Springer, 2009. ISBN 1441902627.

Requirements:
Programming in C, parallel algorithms, computer architectures, principles of pipelining.

Informace o předmětu a výukové materiály naleznete na https://courses.fit.cvut.cz/MI-PAP/

The course is also part of the following Study plans:
Study Plan Study Branch/Specialization Role Recommended semester
MI-SPOL.2016 Unspecified Branch/Specialisation of Study VO 2
MI-WSI-WI.2016 Web and Software Engineering V 2
MI-WSI-SI.2016 Web and Software Engineering V 2
MI-ZI.2016 Knowledge Engineering V 2
MI-ZI.2018 Knowledge Engineering V 2
MI-PSS.2016 Computer Systems and Networks PO 2
MI-SP-SP.2016 System Programming V 2
NI-TI.2018 Computer Science V 2
MI-WSI-ISM.2016 Web and Software Engineering V 2
MI-NPVS.2016 Design and Programming of Embedded Systems V 2
MI-SP-TI.2016 System Programming V 2
MI-PB.2016 Computer Security V 2


Page updated 28. 3. 2024, semester: Z/2023-4, L/2019-20, L/2022-3, Z/2019-20, Z/2022-3, L/2020-1, L/2023-4, Z/2020-1, Z,L/2021-2, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška