A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.
BIE-APS.1 Architectures of Computer Systems Extent of teaching: 2P+2C Instructor: Completion: Z,ZK Department: 18104 Credits: 5 Semester: Z Annotation:
Students will learn the construction principles of internal architecture of computers with universal processors at the level of machine instructions. Special emphasis is given on the pipelined instruction processing and on the memory hierarchy. Students will understand the basic concepts of RISC and CISC architectures and the principles of instruction processing not only in scalar processors, but also in superscalar processors that can execute multiple instructions in one cycle, while ensuring the correctness of the sequential model of programs. The course further elaborates the principles and architectures of shared memory multiprocessor and multicore systems and the memory coherence and consistency in such systems.
Lecture syllabus:
1. Quantitative principles of computer design 2. Instruction Set Architecture (ISA) 3. Introduction to Verilog 4. Single-cycle RISC processor design 5. Pipelined RISC processor design 6. Memory hierarchy: cache memory 7. Memory hierarchy: virtual memory 8. Coherence of shared memory in multiprocessor systems 9. Memory consistency and synchronization primitives 10. Superscalar processors I 11. Superscalar processors II 12. Superscalar processors III Seminar syllabus:
1. Evaluation of computer performance 2. ISA and the MIPS assembly language 3. Programming in assembly language for MIPS 4. Hardware description language (Verilog) 5. Basic components of simple RISC processors 6. Pipelined processor 7. Cache memory viewed by CPU/assembler 8. Cache memory viewed by a C/C++ programmer 9. MESI coherence protocol 10. Memory consistency and synchronization primitives 11. Memory consistency viewed by a C/C++ programmer 12. Superscalar processors 13. Semestral projects check, assessment Literature:
[1] Patterson, D. A. - Hennessy, J. L.: Computer Organization and Design: The Hardware/Software Interface, 4th Edition, Morgan Kaufmann, 2011, 978-0123747501, [2] Hennessy, J. L. - Patterson, D. A.: Computer Architecture: A Quantitative Approach, 5th Edition, Morgan Kaufmann, 2011, 978-0123838728. Requirements:
Basic knowledge of combinational and sequential logical circuits. Knowledge of basic instruction cycle and assembly labguage programming. Programing in C, the role of a compiler for a higher level PL.
Information about the course and courseware are available at https://courses.fit.cvut.cz/BIE-APS/ The course is also part of the following Study plans:
Study Plan Study Branch/Specialization Role Recommended semester BIE-BIT.2015 Computer Security and Information technology (Bachelor, in English) PO 3 BIE-WSI-SI.2015 Software Engineering (Bachelor, in English) V 5 BIE-SI.21 Software Engineering 2021 V 3 BIE-TI.2015_ORIGINAL Computer Science (Bachelor, in English) PO 5 BIE-TI.2015 Computer Science (Bachelor, in English) PO 5
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