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A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The list presented here is sorted by departments, within departments alphabetically by the Course title. The departments are listed alphabetically by the Department code.

Courses


18103 Department of Digital Design
Course code Course title Extent of teaching
Completion
Semester
Credits
Guarantor Instructors
MI-PVS Advanced embedded systems 2+2 Z,ZK Z 4 Skrbek M. Skrbek M.
MI-AAK.1 Arithmetics and Codes 2+2 Z,ZK L 5 Pluháček A. Pluháček A.
MI-AAK Arithmetics and Codes 2+2 Z,ZK L 4
MIE-AAK.1 Arithmetics and Codes 2+2 Z,ZK L 5 Pluháček A. Kubalík P.
MIE-AAK Arithmetics and Codes 2+1 Z,ZK L 4
BI-ZRS Basics of System Control 2+2 Z,ZK Z 4 Hyniová K. Hyniová K.
BIE-ZRS Basics of Systems Control 2+2 Z,ZK L 4 Hyniová K. Hyniová K.
MI-ARI Computer arithmetic 2+1 Z,ZK Z,L 4 Pluháček A. Pluháček A.
MIE-ARI Computer Arithmetic 2+1 Z,ZK Z 4 Kubalík P. Kubalík P.
BI-SAP Computer Structure and Architecture 2+3 Z,ZK L 6 Kubátová H. Kubátová H.
BIK-SAP Computer Structure and Architecture 13+4 Z,ZK L 6 Dobiáš R. Dobiáš R.
BIE-SAP Computer Structures and Architectures 2+3 Z,ZK L 6 Douša J. Douša J.
BIE-JPO Computer Units 2+2 Z,ZK Z 5 Kubalík P., Pluháček A. Kubalík P.
BI-JPO Computer Units 2+2 Z,ZK Z 5 Pluháček A. Pluháček A.
BIK-JPO Computer Units 13+4 Z,ZK Z 5
MIE-NFA Design for the FPGA and ASIC Technology 2+1 Z,ZK Z 4
MIE-NFA.16 Design for the FPGA and ASIC Technology 2+1 Z,ZK Z 5 Schmidt J. Schmidt J.
MI-NFA Design for the FPGA and ASIC Technology 2+1 Z,ZK Z 4
MI-NFA.16 Design for the FPGA and ASIC Technology 2+1 Z,ZK Z 5 Schmidt J. Schmidt J.
BI-CAO Digital and Analog Circuits 2+2 Z,ZK Z 5 Kyncl J., Novotný M. Kyncl J., Novotný M.
BIE-CAO Digital and Analog Circuits 2+2 Z,ZK Z 5 Hyniová K. Daňhel M., Hyniová K.
BIK-CAO Digital and Analog Circuits 13+4 Z,ZK Z 5 Hyniová K. Hyniová K.
MIE-SIM.16 Digital Circuit Simulation 2+1 Z,ZK Z 5 Kohlík M. Kohlík M.
MIE-SIM Digital Circuit Simulation 2+1 Z,ZK Z 4
MI-SIM Digital Circuit Simulation 2+1 Z,ZK Z 4
MI-SIM.16 Digital Circuit Simulation 2+1 Z,ZK Z 5 Douša J., Kohlík M. Kohlík M.
BIE-VES Embedded Systems 2+2 Z,ZK L 5
BIK-VES Embedded Systems 13+4 Z,ZK L 5
BI-VES Embedded systems 2+2 Z,ZK L 5 Skrbek M. Skrbek M.
MI-BKO.16 Error Control Codes 2+1 Z,ZK L 5 Kubalík P., Pluháček A. Kubalík P., Pluháček A.
MIE-BKO.16 Error Control Codes 2+1 Z,ZK L 5 Kubalík P., Pluháček A. Kubalík P.
BI-ZIVS Intelligent Embedded System Fundamentals 1+3 KZ Z 4 Skrbek M. Skrbek M.
MI-IVS Intelligent embedded systems 1+3 KZ L 4 Skrbek M. Skrbek M.
BI-ARD Interactive applications on Arduino 0+3 KZ L 4 Háleček I. Borecký J., Cvrček J., Háleček I., Hánová G., Hülle R., Říha J., Labský D., Wijas J.
MI-OLI Linux Drivers 2+2 Z,ZK L 4 Skrbek M. Skrbek M.
BI-MPP Methods of interfacing peripheral devices 2+2 Z,ZK Z 4 Skrbek M. Skrbek M.
BIE-PNO Practical Digital Design 2+2 KZ Z 5
BIK-PNO Practical Digital Design 13+4 KZ Z 5
BI-PNO Practical Digital Design 2+2 KZ Z 5 Novotný M. Novotný M.
MIE-PAA Problems and Algorithms 2+2 Z,ZK Z 5 Fišer P. Fišer P.
MI-PAA Problems and Algorithms 2+2 Z,ZK Z 5 Schmidt J. Schmidt J.
BIE-SRC Real-time Systems 2+2 KZ L 4 Kubátová H. Kubátová H.
BIK-SRC Real-time Systems 13+4 KZ L 4
BI-SRC Real-time systems 2+2 KZ Z 4 Kubátová H. Kubátová H.
MI-RTS Real-Time Systems 2+1 Z,ZK Z 4
MI-BHW.16 Security and Hardware 2+2 Z,ZK L 5 Novotný M. Novotný M.
MIE-BHW.16 Security and Hardware 2+2 Z,ZK L 5 Novotný M. Novotný M.
MIE-MAS System Modeling and Analysis 2+1 Z,ZK Z 4
MI-MAS System Modeling and Analysis 2+1 Z,ZK Z 4
MIE-SOC Systems on Chip 2+1 Z,ZK Z 4
MIE-SOC.16 Systems on Chip 2+1 Z,ZK Z 5 Kubátová H. Kubátová H.
MI-SOC Systems on Chip 2+1 Z,ZK Z 4
MI-SOC.16 Systems on Chip 2+1 Z,ZK Z 5 Kubátová H. Kubátová H.
MIE-TES.16 Systems Theory 2+1 Z,ZK Z 5 Ratschan S. Ratschan S.
MIE-TES.2 Systems Theory 2+1 Z,ZK Z 4
MI-TES.16 Systems Theory 2+1 Z,ZK Z 5 Ratschan S. Ratschan S.
MI-TES.2 Systems Theory 2+1 Z,ZK Z 4
MIE-TSP Testing and Reliability 2+2 Z,ZK Z 4
MIE-TSP.16 Testing and Reliability 2+2 Z,ZK Z 5 Fišer P. Fišer P.
MI-TSP Testing and Reliability 2+2 Z,ZK Z 4
MI-TSP.16 Testing and Reliability 2+2 Z,ZK Z 5 Fišer P. Fišer P.
BIE-TUR User Interface Design 2+2 Z,ZK L 4 Schmidt J. Schmidt J.
BIK-TUR User Interface Design 13+4 Z,ZK L 4 Schmidt J. Schmidt J.
BI-TUR User Interface Design 2+2 Z,ZK L 4 Schmidt J. Schmidt J.


Page updated 20. 9. 2017, semester: L/2015-6, Z,L/2016-7, Z/2017-8, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška