A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.
BI-JPO.21 Computer Units Extent of teaching: 2P+2C Instructor: Kubalík P. Completion: Z,ZK Department: 18103 Credits: 5 Semester: Z Annotation:
Students deepen their basic knowledge of digital computer units acquired in the obligatory course of the program (BIE-SAP), get acquainted in detail with the internal structure and organization of computer units and processors and their interactions with the environment, including accelerating arithmetic-logic units and using appropriate codes for implementation of multiplication. The organization of main memory and other internal memories (addressable, LIFO, FIFO and CAM) will be discussed in detail, including codes for error detection and correction for parallel and serial data transmissions. They will also get acquainted with the methodology of controller design, with the principles of communication of the processor with the environment and the architecture of the bus system. The problems will be practically evaluated in the labs and with the help of the educational microprogrammed processor simulator and programmable hardware design kits (FPGA).
Lecture syllabus:
1. Digital computer structure and its functional units. 2. Implementation of arithmetic operations. 3. Circuits for arithmetic operations in 2's complement representation. 4. Design of the CPU control unit and controllers. 5. Circuits for multiplication and division. 6. Architecture and principles of memory elements. 7. Realization of memories with different organization and access (addressable, LIFO, FIFO, CAM). 8. [2] Error-detecting and error-correcting codes for memory data transfers: linear codes. 10. Error-detecting and error-correcting codes for serial data transmissions: cyclic codes. 11. I/O units and their control. 12. Data paths, buses - their types, modes, arbitration. 13. Circuits for floating-point operations. Seminar syllabus:
1. Number systems, conversions and operations. 2. Representations of negative numbers. 3. Simple processor - instructions, machine code, data part. 4. Simple processor - instruction cycle, interface. 5. Simple processor - microprogramming. 6. Simple processor - demonstration of a microprogram. 7. Wired controller design I. 8. Wired controller design II. 9. Linear codes. 10. Cyclic codes. 11. Design of a processor component on FPGA. 12. Demonstration of the designed processor component. 13. Spare seminar, assessment. Literature:
1. Hennesy, J. L., Patterson, D. A. ''Computer Architecture: A Quantitative Approach (6th Edition)''. Morgan Kaufmann, 2017. ISBN 9780128119051. 2. Tanenbaum, A. S. ''Structured Computer Organization (6th Edition)''. Prentice Hall, 2013. ISBN 9780132916523. 3. Stallings, W. ''Computer Organization and Architecture: Designing for Performance (10th Edition)''. Prentice Hall, 2016. ISBN 9780134101613. 4. Hamacher, C., Vranesic, Z., Zaky, S. ''Computer Organization (5th Edition)''. McGraw-Hill, 2011. ISBN 9781259005275. Requirements:
Entry knowledge: Basic knowledge of the structure and architecture of a digital computer, design principles for combinational and sequential circuits, binary arithmetic, the concept of computer memory.
Informace o předmětu a výukové materiály naleznete na https://courses.fit.cvut.cz/BI-JPO/
Na tento předmět navazuje v magisterském studiu předmět Počítačová aritmetika.The course is also part of the following Study plans:
Page updated 19. 4. 2024, semester: L/2020-1, L/2021-2, Z/2023-4, Z/2024-5, Z/2019-20, Z/2022-3, L/2019-20, L/2022-3, Z/2020-1, Z/2021-2, L/2023-4, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška