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A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.

BIK-APS.21 Architectures of Computer Systems Extent of teaching: 14KP+4KC
Instructor: Štepanovský M. Completion: Z,ZK
Department: 18104 Credits: 5 Semester: Z

Annotation:
Students will learn the construction principles of internal architecture of computers with universal processors at the level of machine instructions. Special emphasis is given on the pipelined instruction processing and on the memory hierarchy. Students will understand the basic concepts of RISC and CISC architectures and the principles of instruction processing not only in scalar processors, but also in superscalar processors that can execute multiple instructions in one cycle, while ensuring the correctness of the sequential model of the program. The course further elaborates the principles and architectures of shared memory multiprocessor and multicore systems and the memory coherence and consistency in such systems.

Lecture syllabus:
1. Quantitative principles of computer design, Amdahl?s law, computer performance evaluation, benchmarks.
2. Instruction set architectures: taxonomy RISC processors vs. CISC processors, assembly language.
3. Verilog as a hardware description language: syntax and semantics.
4. Incremental design of a single-cycle RISC processor, principles and basic implementations of CPU control units.
5. Design of a simple pipelined RISC processor, hazards in the pipeline and their elimination.
6. Memory hierarchy: Cache memory principle, various implementations (direct-mapped, fully associative, N-way set-associative).
7. Memory hierarchy: Virtual memory (paging) and its HW support in memory management units of conventional CPUs.
8. Multicore CPUs and multiprocessor systems. Cache memory coherence, the MESI protocol, directory-based coherence.
10. Memory consistency and the sequential consistency model. Synchronization instructions for accessing shared memory.
11. Superscalar CPUs I: Introduction to instruction-level parallelism. Static (in-order) and dynamic (out-of-order) instruction execution, register renaming (Tomasulo's algorithm).
12. Superscalar CPUs II: Memory-referencing instructions, load bypassing and load forwarding, speculative loads from memory. Memory consistency for multi-core CPUs.
13. Superscalar CPUs III: Branch prediction, speculative instruction prefetching and execution.

Seminar syllabus:
1. Evaluation of computer performance
2. ISA and the MIPS assembly language
3. Programming in assembly language for MIPS
4. Hardware description language (Verilog)
5. Basic components of simple RISC processors
6. Pipelined processor
7. Cache memory viewed by CPU/assembler
8. Cache memory viewed by a C/C++ programmer
9. MESI coherence protocol
10. Memory consistency and synchronization primitives
11. Memory consistency viewed by a C/C++ programmer
12. Superscalar processors
13. Semestral projects check, assessment

Literature:
1. Patterson D. A., Hennessy J. L. : Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2014. ISBN 978-0128012857.
2. Hennessy J.L., Patterson D.A. : Computer Architecture: A Quantitative Approach (6th Edition). Morgan Kaufmann, 2017. ISBN 978-0128119051.
3. Shen J. P., Lipasti M. H. : Modern Processor Design. Fundamentals of Superscalar Processors. Waveland Press, 2013. ISBN 978-1478607830.

Requirements:
Basic knowledge of combinational and sequential logical circuits. Knowledge of basic instruction cycle and assembly labguage programming. Programing in C, the role of a compiler for a higher level PL.

Chybí klíčová slova: Informace o předmětu a výukové materiály naleznete na https://courses.fit.cvut.cz/BI-APS/
Na tento předmět navazuje v magisterském studiu předmět Pokročilé architektury počítačových systémů a také Virtualizace a cloud computing.

The course is also part of the following Study plans:
Study Plan Study Branch/Specialization Role Recommended semester
BIK-PV.21 Computer Systems and Virtualization 2021 (in Czech) PS 3
BIK-IB.21 Information Security 2021 (in Czech) PS 3
BIK-SPOL.21 Unspecified Branch/Specialisation of Study VO 3
BIK-PS.21 Computer Networks and Internet 2021 (in Czech) PS 3


Page updated 29. 3. 2024, semester: L/2021-2, Z,L/2023-4, Z/2021-2, Z/2020-1, Z/2019-20, L/2020-1, Z,L/2022-3, L/2019-20, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška