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A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.

MI-NFA.16 Design for the FPGA and ASIC Technology Extent of teaching: 2P+1C
Instructor: Completion: Z,ZK
Department: 18103 Credits: 5 Semester: Z

Annotation:
Students gain the basic knowledge needed to start a career in a design house. They will understand the FPGA and ASIC implementation technologies and the limitations that the technologies impose on the design. They are able to perform and to manage typical workflows, their analytic and synthetic steps, with an emphasis on basic verification. They know the structure and demands of software tools, as well as what to expect from them.

Lecture syllabus:
1. The gist of hardware design. The role and types of decomposition. Synthetic and analytic steps. Basic economy of product design and manufacturing.
2. CMOS circuits, dynamic behavior, power consumption. Technology characterization. Implementation of programmable combinational function and programmable interconnect.
3. Synchronous digital design, timing, models. Clock domains, signal transfer across clock domain boundary. Metastablility.
4. Top-down and bottom-up design process, its steps and iteration loops. Hardware project management, metrics. Intellectual property cores. Reuse methodology.
5. Programmable devices: overview, usage, programming methods. SPLD and CPLD devices.
6. FPGA devices: architecture, logical blocks, interconnect, blocks performing computation and communication, memory blocks. Dynamic behavior.
7. Design styles for ASICs. The impact of deep submicron technologies. ASIC design tools.
8. ASIC and FPGA workflow comparison, key differences.
9. Verification techniques: formal techniques (model checking, equivalence checking), advanced simulation, assertions, hybrid assertion-based techniques.
10. Physical design: routing, placement, technology mapping.
11. Logic synthesis, basic phases, used formalisms. Timing-driven and power-driven synthesis.
12. Behavioral synthesis, areas of use.
13. System-level design, hardware-software decomposition and codesign, design by model refinement.

Seminar syllabus:
1. Lab: getting started with equipment, software and kits
2. Lab: synchronous FPGA design
3. Lab: synchronous FPGA design
4. Lab: FPGA design with multiple clock domains
5. Lab: FPGA design with multiple clock domains
6. Lab: FPGA design with multiple clock domains
7. Lab: FPGA design with given speed and external timing
8. Lab: FPGA design with given speed and external timing
9. Lab: FPGA design with given speed and external timing
10. Lab: verification
11. Lab: verification
12. Lab: verification
13. Lab: verification
14. Presentation of results, evaluation

Literature:
1. Wilson, P. ''Design Recipes for FPGAs''. Newnes, 2007. ISBN 0750668458.

Requirements:
Gates and registers, basic CMOS circuits, simple gate-level design, finite state machine and its synchronous implementation.

Informace o předmětu a výukové materiály naleznete na https://moodle-vyuka.cvut.cz/course/view.php?id=2211

The course is also part of the following Study plans:
Study Plan Study Branch/Specialization Role Recommended semester
MI-SPOL.2016 Unspecified Branch/Specialisation of Study VO 1
MI-WSI-WI.2016 Web and Software Engineering V 1
MI-WSI-SI.2016 Web and Software Engineering V 1
MI-ZI.2016 Knowledge Engineering V 1
MI-ZI.2018 Knowledge Engineering V 1
MI-PSS.2016 Computer Systems and Networks V 1
MI-SP-SP.2016 System Programming V 1
MI-NPVS.2016 Design and Programming of Embedded Systems PO 1
NI-TI.2018 Computer Science V 1
MI-WSI-ISM.2016 Web and Software Engineering V 1
MI-SP-TI.2016 System Programming V 1
MI-PB.2016 Computer Security V 1


Page updated 28. 3. 2024, semester: Z/2023-4, L/2019-20, L/2022-3, Z/2019-20, Z/2022-3, L/2020-1, L/2023-4, Z/2020-1, Z,L/2021-2, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška