A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.
MI-MCS Multicore Systems Extent of teaching: 1P+2C Instructor: Completion: KZ Department: 18104 Credits: 4 Semester: Z Annotation:
Students understand architecture of systems based on multicore processors with multiple threads per core, structure and usage of cache hierarchy with shared last level. They learn parallel algorithm classification, parallel programming technics, simulation and monitoring tools for measurement and optimization of parallel algorithms. After this course, students can design MTMD programs (Multiple Threads Multiple Data), measure and analyze latency and throughput of parallel algorithms and optimize them for contemporary multicore systems.
Lecture syllabus:
1. Multiprocessor systems, multicore processors, multithreaded processor cores. Hierarchy of caches in multicore processor, cache coherency protocols. 2. Synchronization primitives and data consistency in multiprocessor systems, memory models. 3. Parallel programming patterns for MTMD model, parallel data structures and algorithms and their behavior and optimization on multicore systems with multiple cache layers (cache conscious programming). 4. Methods of parallel algorithms measurement and optimization. 5. Parallel methods properties: deadlock-free, starvation-free, lock-free, wait-free. 6. Operating system impact on parallel program performance and its elimination. Critical path and its optimization. Seminar syllabus:
1. Tutorial: Measurement of Intel cache hierarchy base properties. 2. Tutorial: Simulation of simple parallel algorithms. 3. Project assignment: measurement, simulation, evaluation and optimization of parallel algorithms. 4. Consultation. 5. Consultation. The 1st project checkpoint. 6. Consultation. 7. The 1st project results. 8. Consultation. Sponsors project assignment. 9. Consultation. The 2nd project checkpoint. 10. Consultation. 11. Consultation. 12. The 2nd project results. 13. The sponsors project results. Literature:
1. Maurice Herlihy, Nir Shavit: The Art of Multiprocessor Programming. 2. Rauber, Thomas and Rünger, Gudula: Parallel Programming Models, Springer, 2010 3. David A. Patterson, John L. Hennessy: Computer Organization and Design: The Hardware/Software Interface, Fourth Edition 4. Ricardo Bianchini, Enrique V. Carrera and Leonidas Kontothanassis: Evaluating the Effect of Coherence Protocols on the Performance of Parallel Programming Constructs, 1998 5. Ricardo Bianchini, Leonidas Kontothanassis: Algorithms for Categorizing Multiprocessor Communication Under Invalidate and Update-Based Coherence Protocols, 1995 6. Bryan R. Buck,Jeffrey K. Hollingsworth: Using Hardware Performance Monitors to Isolate Memory Bottlenecks, 2000 Requirements:
1. programming skills (assembler, C/C++ or C#), 2. OS Linux/Windows, networking, 3. BI-EIA, MI-PAP and MI-PAR are advantageous, but not strictly required.
Informace o předmětu a výukové materiály naleznete na https://moodle-vyuka.cvut.cz/course/view.php?id=2024 The course is also part of the following Study plans:
Study Plan Study Branch/Specialization Role Recommended semester MI-ZI.2016 Knowledge Engineering V Není MI-ZI.2018 Knowledge Engineering V Není MI-SP-TI.2016 System Programming V Není MI-SP-SP.2016 System Programming V Není MI-SPOL.2016 Unspecified Branch/Specialisation of Study V Není MI-WSI-WI.2016 Web and Software Engineering V Není MI-WSI-SI.2016 Web and Software Engineering V Není MI-WSI-ISM.2016 Web and Software Engineering V Není MI-NPVS.2016 Design and Programming of Embedded Systems V Není MI-PSS.2016 Computer Systems and Networks V Není MI-PB.2016 Computer Security V Není MI-WSI-ISM.2016 Web and Software Engineering V 3 NI-TI.2018 Computer Science V 1,3
Page updated 25. 4. 2024, semester: Z,L/2023-4, Z/2019-20, Z/2024-5, L/2022-3, Z/2020-1, Z,L/2021-2, L/2020-1, Z/2022-3, L/2019-20, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška