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For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.

BIE-SAP Computer Structures and Architectures Extent of teaching: 2P+1R+2C
Instructor: Completion: Z,ZK
Department: 18103 Credits: 6 Semester: L

Annotation:
Students understand basic digital computer units and their structures, functions, and hardware implementation: ALU, control unit, memory system, inputs, outputs, data storage and transfer. In the labs, students gain practical experience with the design and implementation of the logic of a simple processor using modern digital design tools.

Lecture syllabus:
1. Introduction, basic architecture of a computer, data representation.
2. Logic functions and their descriptions, combinational circuits, implementation using gates.
3. Sequential circuits. Synchronous design, implementation using gates and flip-flops. Mealy and Moore automata.
4. Typical circuit components of a computer, their implementations (encoder, adder, counter, register).
5. Arithmetic operations with numbers in fixed-point representation.
6. Architecture of the AVR processor; machine code and assembler.
7. Implementation of arithmetic operations with numbers in foating point. representation.
8. Processor data path; arithmetic and logic unit.
9. Memories - memory cell structure, static and dynamic memories, LIFO & FIFO memories.
10. Buses & interrupts.
11. Memory hierarchical system, cache memory.
12. Processor control units, RISCs & CISC processors.

Seminar syllabus:
1. Adders, gates, practical implementation.
2. Boolean algebra, minimization, gates.
3. Combinatorial circuits, converters.
4. Minimization, gate-level design, logic functions.
5. Sequential circuits, counter, sequence matching.
6. Sequential design, graph of transitions, table, implementation using D-type flip-flops and gates.
7. Architecture of the AVR processor, sample program.
8. Arithmetics, addition, negative numbers, overflow, complement code.
9. Program - shifts, ASCII.
10. Test, project assignment. Assembler.
11. Project work - display.
12. Arithmetic programs, shifts, control of peripherals.
13. Project result presentations.

Literature:
1. Douša, J., Pluháček, A. "Introduction to Computer Systems". Praha: ČVUT, 2000. ISBN 80-01-02103-3.
2. Gajski, D. D. "Principles of Digital Design". Prentice Hall, 1996. ISBN 0133011445.
3. Friedman, A. D., Menon, P. R. "Theory and Design of Switching Circuits". Computer Science Press, 1975. ISBN 0914894528.
4. McCluskey, E. J. "Logic Design Principles". Prentice-Hall, 1986. ISBN 0135397685.
5. Sasao, T. "Switching Theory for Logic Synthesis". Springer, 1999. ISBN 0792384563.
6. http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-111Introductory-Digital-Systems-LaboratoryFall2002/CourseHome/index.htm

Requirements:
Basic knowledge of physical principles of digital circuits (transistors as switches, implementation of registers, data storage principles) and fundamentals of discrete mathematics (number representation systems, Boolean algebra).

Information about the course and courseware are available at https://courses.fit.cvut.cz/BIE-SAP/

The course is also part of the following Study plans:
Study Plan Study Branch/Specialization Role Recommended semester
BIE-TI.2015_ORIGINAL Computer Science (Bachelor, in English) PP 2
BIE-BIT.2015 Computer Security and Information technology (Bachelor, in English) PP 2
BIE-TI.2015 Computer Science (Bachelor, in English) PP 2
BIE-WSI-SI.2015 Software Engineering (Bachelor, in English) PP 2


Page updated 19. 4. 2024, semester: L/2020-1, L/2021-2, Z/2023-4, Z/2024-5, Z/2019-20, Z/2022-3, L/2019-20, L/2022-3, Z/2020-1, Z/2021-2, L/2023-4, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška