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A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.

BI-PNO Practical Digital Design Extent of teaching: 2P+2C
Instructor: Novotný M. Completion: KZ
Department: 18103 Credits: 5 Semester: Z

Annotation:
Students get an overview of the contemporary digital design flow and learn practical skills to use synchronous design techniques. They understand the basics of the VHDL language, and implementation technologies FPGA and ASIC. Students demonstrate practical use of the design techniques in the module project sing modern, industry-standard CAD design tools.

Lecture syllabus:
1. Contemporary digital design flow.
2. Project management, metrics, and estimates.
3. Fundamentals of synchronous design.
4. Digital circuits implementation technologies - ASICs, FPGAs.
5. Design at the algorithm level, decomposition to blocks.
6. VHDL language for the description of digital circuits.
7. Circuit description on the RT level - registers, counters, multiplexers.
8. Circuit description on the RT level - arithmetics.
9. Circuit description on the RT level - on-chip memories.
10. Synthesis from RT level - the use of constraints.
11. Verification plan, models of verification.
12. Implementation of a testbench.
13. Design for testability.

Seminar syllabus:
1. Students will get practical experience in the design of digital circuits using EDA tools for FPGAs. Students will work out a semestral project and accomplish a short visit in a professional design center.
2. Introduction to the subject.
3. [3] Introduction and exercises with FPGA EDA tool.
4. [3] Design and verification of a simple synchronous circuit.
5. [5] Individual work on the semestral project.
6. Visit to a professional digital design center.
7. Presentation of the results.
8. Evaluation.

Literature:
Ashenden, P. J. The designer's guide to VHDL, 3rd Edition. Morgan Kaufmann, 2008. ISBN 0120887851.

Requirements:
Basic knowledge of architectures of computers and their units and of digital system design techniques.

Informace o předmětu a výukové materiály naleznete na https://courses.fit.cvut.cz/BI-PNO/

The course is also part of the following Study plans:
Study Plan Study Branch/Specialization Role Recommended semester
BI-WSI-WI.2015 Web and Software Engineering V 5
BI-WSI-PG.2015 Web and Software Engineering V 5
BI-WSI-SI.2015 Web and Software Engineering V 5
BI-SPOL.2015 Unspecified Branch/Specialisation of Study VO 5
BI-ZI.2018 Knowledge Engineering V 5
BI-PI.2015 Computer engineering PO 5
BI-BIT.2015 Computer Security and Information technology V 5
BI-TI.2015 Computer Science V 5
BI-ISM.2015 Information Systems and Management V 5


Page updated 28. 3. 2024, semester: Z/2023-4, L/2019-20, L/2022-3, Z/2019-20, Z/2022-3, L/2020-1, L/2023-4, Z/2020-1, Z,L/2021-2, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška