A course is the basic teaching unit, it's design as a medium for a student to acquire comprehensive knowledge and skills indispensable in the given field. A course guarantor is responsible for the factual content of the course.
For each course, there is a department responsible for the course organisation. A person responsible for timetabling for a given department sets a time schedule of teaching and for each class, s/he assigns an instructor and/or an examiner.
Expected time consumption of the course is expressed by a course attribute extent of teaching. For example, extent = 2 +2 indicates two teaching hours of lectures and two teaching hours of seminar (lab) per week.
At the end of each semester, the course instructor has to evaluate the extent to which a student has acquired the expected knowledge and skills. The type of this evaluation is indicated by the attribute completion. So, a course can be completed by just an assessment ('pouze zápočet'), by a graded assessment ('klasifikovaný zápočet'), or by just an examination ('pouze zkouška') or by an assessment and examination ('zápočet a zkouška') .
The difficulty of a given course is evaluated by the amount of ECTS credits.
The course is in session (cf. teaching is going on) during a semester. Each course is offered either in the winter ('zimní') or summer ('letní') semester of an academic year. Exceptionally, a course might be offered in both semesters.
The subject matter of a course is described in various texts.
BI-CAO Digital and Analog Circuits Extent of teaching: 2P+2C Instructor: Completion: Z,ZK Department: 18103 Credits: 5 Semester: Z Annotation:
Students get the fundamental understanding of technologies underlying electronic digital systems. They understand the basic theoretical models and principles of functionality of transistors, gates, circuits, and conductors. They are able to design simple circuits and evaluate circuit parameters. They understand the differences between analog and digital modes of electronic devices.
Lecture syllabus:
1. Introduction. Voltage, current. Voltage and current sources. Ideal conductor. 2. Resistor, capacitor, inductor. Introduction to Node voltage method. 3. Node voltage method. DC circuits. 4. RC element. Serial and parallel connection of equivalent elements. Voltage divider. Power. 5. Digital circuits. 6. Transistors. Digital circuits. 7. Digital circuits. Introduction to Sinusoidal steady state. 8. Sinusoidal steady state. Phasors, impedance, transfer, decibels. 9. Sinusoidal steady state. Transfer, decibels, power. 9. Resonant circuits. Fourier series. 11. Homogeneous transmission line, reflections. Magnetically coupled circuits. Transformers. 12. Operational amplifiers. Runge-Kutta method. Seminar syllabus:
1. Introduction to SW Mathematica, solving of various types of equations. 2. Introduction to SW Mathematica. 3. TEST1. Node voltage method. 4. Node voltage method. 5. Node voltage method. 6. DC circuits. Transistors. 7. TEST2. Introduction of sinusoidal steady state. 8. Single-frequency sinusoidal steady state. 9. Sinusoidal steady state - impedance. transfer function. 10. Sinusoidal steady state - impedance. transfer function, power. 11. TEST3. 12. Assesment. 13. Reserve. Literature:
Requirements:
High-School level of mathematics and physics.
Informace o předmětu a výukové materiály naleznete na https://courses.fit.cvut.cz/BI-CAO/ The course is also part of the following Study plans:
Study Plan Study Branch/Specialization Role Recommended semester BI-SPOL.2015 Unspecified Branch/Specialisation of Study PP 1 BI-WSI-PG.2015 Web and Software Engineering PP 1 BI-WSI-WI.2015 Web and Software Engineering PP 1 BI-WSI-SI.2015 Web and Software Engineering PP 1 BI-ISM.2015 Information Systems and Management PP 1 BI-ZI.2018 Knowledge Engineering PP 1 BI-PI.2015 Computer engineering PP 1 BI-TI.2015 Computer Science PP 1 BI-BIT.2015 Computer Security and Information technology PP 1
Page updated 20. 4. 2024, semester: L/2023-4, L/2020-1, L/2022-3, L/2021-2, Z/2019-20, Z/2022-3, Z/2020-1, Z/2023-4, L/2019-20, Z/2021-2, Z/2024-5, Send comments to the content presented here to Administrator of study plans Design and implementation: J. Novák, I. Halaška